application note mk5025 synchronous timing introduction the sgs-thomson mk5025 x.25 link level controller is a vlsi device which provides a com- plete link level data communication control con- forming to the 1984 ccitt version of x.25. the mk5025 also supports x.32 (xid) and x.75 as well as single channel lapd for isdn with its ui frames and extended addressing capabilities. purpose although the mk5025 data sheet and technical manual provide detailed asynchronous timing dia- grams that specifiy the relationships of the host interface signals to one another, the designer may often find it helpful to know how these timing values relate to the system clock. the purpose of this application brief is to provide a description of the mk5025 host interface as related to sysclk (mk5025 pin 28). because of the asynchronous nature of the use of this device, the mk5025 production testing is per- formed to ensure compliance with the asynchro- nous timing specifications stated in the data sheet and technical manual. it should be noted that although the synchronous timing diagrams in this document are provided to facilitate the design process, the timing requirements in the data sheet must still be met to ensure proper op- eration. AN494/0592 sysclk adr das read (write) dal0-15 data in >40ns >40ns >30ns >20ns >20ns <80ns <45ns >30ns cs ready >40ns >30ns >40ns >35ns 1. input setup and hold times are in italics. these times are typical minimum values required to or from the particular edge specified in order to be recognized in that cycle. 2. output delay times are the typical maximum delay from the specified edge to a valid output. notes: figure 1: mk5025 bus slave write cycle 1/5
synchronous timing the synchronous timing data contained within this document was derived from a sample of mk 5025 devices and guard-banded to allow for process variations. although these values are not guaran- teed or tested in the manufacturing process, the typical mk5025 device performance should meet or exceed these timing values. figures 1 and 2 provide the typical timing relation- ships, with respect to sysclk, for the mk 5025 operating as a bus slave. figures 3 and 4 pro- vide the typical timing relationships, with respect to sysclk, for the mk5025 operating as a bus master. the input setup and hold times given in this docu- ment are typical minimum values required to or from the sysclk edge indicated in order to be recognized within that sysclk cycle. the output delay times are the typical maximum delay from the indicated edge to a valid output state. conclusion the mk5025 offers great flexibility to the data communications system designer. the on-chip protocol processing may be used to save the de- signer much time in implementing standard proto- cols such as x.25, lapb, isdn lapd, x.32, and x.75, and these synchronous timing diagrams are provided to further facilitate the design process. sysclk adr ready dal >40ns >40ns >40ns data out >30ns >30ns >35ns cs das read (read) 0-15 >40ns >30ns <45ns <80ns <20ns >30ns 1. input setup and hold times are in italics. these times are typical minimum values required to or from the particular edge specified in order to be recognized in that cycle. 2. output delay times are the typical maximum delay from the specified edge to a valid output. notes: figure 2: mk5025 bus slave read cycle application note 2/5
a 16-23 as sysclk data addr address dal0-15 read bm0,1 <65ns <65ns <55ns <55ns >25ns notes: 1. the typical mk5025 device performance should meet or exceed the typical timing values given above. asynchronous timing requirements given in the technical manual still apply. 2. input setup and hold times are in italics. these times are typical minimum values required to or from the particular edge specified in order to be recognized in that cycle. 3. output delay times are the typical maximum delay from the specified edge to a valid output. <65ns ready >25ns dalo dali das hold hlda <70ns single dma <65ns burst dma or <55ns <55ns figure 3: mk5025 bus master write cycle application note 3/5
a 16-23 as sysclk data in addr address dal0-15 read bm0,1 <65ns <65ns <55ns <55ns <55ns >25ns >25ns >25ns <70ns single dma or <65ns burst dma <70ns <45ns <65ns ready das dalo dali hlda hold >55ns notes: 1. the typical mk5025 device performance should meet or exceed the typical timing values given above. asynchronous timing requirements given in the technical manual still apply. 2. input setup and hold times are in italics. these times are typical minimum values required to or from the particular edge specified in order to be recognized in that cycle. 3. output delay times are the typical maximum delay from the specifed edge to a valid output. <55ns figure 4: mk5025 bus master read cycle application note 4/5
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics as sumes no responsibi lity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. spec ifications men- tioned in this publication are subject to ch ange without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical c omponents in life support devi ces or systems wi thout ex- press written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies aust ralia - brazil - france - germany - hong kong - i taly - japan - korea - malay sia - malta - morocco - the netherlands - s ingapore - spain - sweden - switzerland - taiwan - thaliand - united k ingdom - u.s.a. application note 5/5
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